Prof. Saurabh Chaudhury

Saurabh-Chaudhury

Professor
Email: saurabh[at]nits[dot]ac[dot]in
Date of Joining: 03/06/1997
Academic/Industrial Experience: 25+ years
Google Scholar: Click Here

AREA OF INTEREST AND SPECIALIZATION (INCLUDING RESEARCH AREA)

  • Semiconductor Devices and Modelling
  • Nanomaterials
  • Low Power VLSI
  • Nanoelectronics-Carbon nanotubes and Nanowires
  • Image Processing
  • Digital Electronics
  • Embedded Systems and Applications

SHORT BIOGRAPHICAL SKETCH

Dr. Saurabh Chaudhury was born in Debipur village under Silchar Sub-division in 1971. Graduated from REC Silchar (now NIT Silchar) with Honours in Electrical Engineering in 1993-94 after his schooling from BNMP Higher Secondary School Dholai in 1989. He joined as a lecturer in REC Silchar in 1997, after a brief experience in industry (one year) and teaching (one year). Subsequently he has obtained his M.Tech and Ph.D degree from IIT Kharagpur in the field of Microelectronics & VLSI design in 2001 and 2009 respectively, through QIP program, Govt. of India. He has always strived for knowledge and research and dreams big. He is working in the domain of low power VLSI design, synthesis, leakage minimization, CNTs and image processing. He has completed one AICTE (RPS) project worth Rs. 8 lacs, as the Principal Investigator and reviewed many papers in technical journals including IEEE, IET and international conferences.

SUBJECTS TAUGHT (INCLUDING SUBJECTS CURRENTLY TEACHING)

  • Digital Signal Processing
  • Image Processing & Computer Vision
  • Digital Electronics
  • Embedded Systems and Applications
  • COA

PROFESSIONAL MEMBERSHIPS

  • Member, IEEE

AWARDS & RECOGNITIONS

  • Best Paper Award offered by Intel Corporation with a Travel Grant of US$ 500.00, +Reg. Fee waiver, to visit Cairns, Australia in ACM Conference 2006.
  • Travel Grant of Rs. 20000.00 from IIT Kharagpur, to visit Singapore with ISIC 2007.
  • Name included in World Who’s Who in 2008.
  • Elevated to Senior Member, IEEE in May 2016.
  • IETE GOURI Memorial Award 2018 for the Best Paper (Review Article in Taylor and Francis).
  • Selected as Fellow of IEI in 2020. Awarded Distinguished Faculty 2020 by NIT Silchar.

ADMINISTRATIVE RESPONSIBILITY

INTERNATIONAL JOURNALS

  1. Neerja Dharmale, Saurabh Chaudhury, Jayanta Kumar Kar, “Various Exchange-Correlation Effects on Structural, Electronic, and Optical Properties of Brookite TiO2”, ECS-Journal-of-Solid-State-Science-and-Technology, 10(8), 2021 DOI: http://dx.doi.org/10.1149/2162-8777/ac1c58.
  2. Jayanta Kumar Kar, Neerja Dharmale, Saurabh Chaudhury, “DFT based studies on the structural, electronic and optical properties of LiNbO3 using some hybrid techniques” Physica Sripta, Vol.96, No. 12, 2021. https://doi.org/10.1088/1402-4896/ac36e9
  3. Neerja Dharmale, Saurabh Chaudhury, Jayant Kar, “Pressure-Induced Phase Transition Study on Brookite to Rutile TiO2 Transformation”, ECS Journal of Solid State Science and Technology, 2021, 10 071021
  4. Neerja Dharmale, Saurabh Chaudhury, Rupesh Mahamune and Debashish Dash, “Comparative study on structural, electronic, optical and mechanical properties of normal and high pressure phases titanium dioxide using DFT”, Materials Research Express, Vol.7, No.5 (SCIE)
  5. Neerja Dharmale, Saurabh Chaudhury and Debashish Dash,”Investigating the Naturally Occurring Forms of TiO2 on Electronic and Optical Properties Using OLCAO-MGGA-TBO9: A Hybrid DFT Study”, Modelling and Simulation in Materials Science and Engineering, 2020 (SCIE), Accepted
  6. Ksh. Robert Singh and Saurabh Chaudhury, “A comparative Analysis of Texture Feature Extraction Techniques for Rice Grain Classification”. IET Image Processing, ACCEPTED (SCI+SCOPUS) 2020
  7. Ksh. Robert Singh and Saurabh Chaudhury, “Classification of Rice Grain Using Wavelet Decomposition: A comparative study”. Journal of Engineering Science and Technology, 2020, vol-15(1),pp. 108-127 (ESCI+SCOPUS)
  8. Ksh. Robert Singh and Saurabh Chaudhury, “Adaptive threshold back propagation neural network for rice grain classification using variance and co-variance colour features”. Journal of mechanics of continua and mathematical sciences, 2019, vol-14(5), pp. 419-436 (ESCI)
  9. KR Singh, S Chaudhury,”A cascade network for the classification of rice grain based on single rice kernel”, Complex & Intelligent Systems, 1-14, 2020
  10. CK Pandey, A Singh, S Chaudhury, ” Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances”, Applied Physics A 126 (3), 1-12, 2020
  11. Singh, A., Chaudhury, S., Sharma, S.M. and Sarkar C.K., “Improved Drive Capability of Silicon Nano Tube Tunnel FET Using Halo Implantation,” in Silicon 2020, https://doi.org/10.1007/s12633-019-00350-y
  12. KSH R SINGH, S CHAUDHURY, “CLASSIFICATION OF RICE GRAIN USING WAVELET DECOMPOSITION: A COMPARATIVE STUDY”, Journal of Engineering Science and Technology 15 (1), 108-127, 2019
  13. Avtar Singh, Chandan K. Pandey, Saurabh Chaudhury, Chandan K. Sarakar, “Design and analysis of High K Silicon Nano Tube Tunnel FET Device” ( in IET Circuits, Devices & Systems, Oct. 2019,.DOI: https://doi.org/10.1049/iet-cds.2019.0230
  14. Chandan K. Pandey, Debashish Dash, and Saurabh Chaudhury, “Approach to suppress ambipolar conduction in Tunnel FET using dielectric pocket,” IET Micro & Nano Letters, Vol. 14, No. 1, 2019 (DOI: 10.1049/mnl.2018.5276). (SCIE, Impact Factor: 0.841)
  15. Debashish Dash, Chandan K. Pandey, Saurabh Chaudhury and Susanta K. Tripathy, “Structural, Electronic, and Mechanical Properties of Anatase Titanium Dioxide – An Ab-Initio Approach,” Multidiscipline Modelling in Materials and Structures, Emerald Publications, 2018 (DOI: 10.1108/MMMS-03-2018-0043). (ESCI, Scopus Indexed) (In Press)
  16. Debashish Dash, Chandan K. Pandey, Saurabh Chaudhury and Susanta K. Tripathy, “Determination of Different Optical Properties for Cubic Titanium Dioxide: An ab-initio Approach,” Advances in Science and Technology Research Journal, Vol. 12, No. 3, 2018 (ESCI Indexed)
  17. Chandan K. Pandey, Debashish Dash, and Saurabh Chaudhury, “Impact of Dielectric Pocket on Analog and High-Frequency Performances of Cylindrical Gate-All-Around Tunnel FETs,” ECS Journal of Solid State Science and Technology, The Electrochemical Society, Vol. 7, No. 5, 2018 (DOI: 10.1149/2.0101805jss). (SCIE, Impact Factor: 1.808)
  18. Debashish Dash, Chandan K Pandey, Saurabh Chaudhury and Susanta K Tripathi, “Structure, Stability and Electronic Properties of Thin TiO2 Nanowires of Different Novel Shapes:An Ab- initio Study” (Accepted) in Transaction on Nanotechnology, Scientia Iranica 2019 (SCIE)
  19. Inaml Hossain and Saurabh Chaudhury, “CNFET based Low Power Full Adder Circuit for VLSI Applications” accepted in Nanoscience & Nanotechnology-Asia, Bentham Science 2019
  20. Avtar Singh, Chandan Kumar Pandey, Saurabh Chaudhury, Chandan Kumar Sarkar, “Effect of Strain in Silicon Nanotube FET devices for Low Power Applications” Europian Journal of Applied Physics (SCI) (accepted) 2019
  21. Avtar Singh, Arpan Dasgupta, Rahul Das, Atanu Kundu, Saurabh Chaudhury, “An Extensive Study of Different Underlap Architectures of sub-32nm DG MOSFET,” IJNEAM, 2018, (Scopus)
  22. Debashish Dash, Chandan Kumar Pandey, Saurabh Chaudhury and S.K. Tripathi [2017], Structural, Electronic, and Mechanical Properties of Cubic TiO2: A First- Principle Study. Chinese Physics B 27 (1), 017102, 2017
  23. Abdul Kayom Md Khairuzzaman and Saurabh Chaudhury [2017], Moth-Flame Optimization Algorithm Based Multilevel Thresholding for Image Segmentation. International Journal of Applied Metaheuristic Computing (IJAMC) 8(4) , 2017.
  24. Rohit Lorenzo and Saurabh Chaudhury [2017], A Novel 9T SRAM Architecture for Low Leakage and High Performance” in Analog Integrated Circuits & Signal Processing (ALOG), Springer (Accepted) 2017
  25. Abdul Kayom Md Khairuzaman and Saurabh Chaudhury [2017], “Multilevel thresholding using grey wolf optimizer for image segmentation” (Accepted in) Expert Systems With Applications, April 2017
  26. Jayesh Ruikar, Ashoke Sinha and Saurabh Chaudhury [2017], “Image Quality Assessment using Edge Correlation”, International Journal of Electronics and Telecommunications, Vol. 63, No. 1 (2017)
  27. Rohit Lorenzo and Saurabh Chaudhury (2016), Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits, Circuits, Systems and Signal Processing (CSSP) Springer. DOI 10.1007/s00034-016-0442-0.
  28. Rohit Lorenzo and Saurabh Chaudhury (2016), “A Novel SRAM cell architecture with Body-bias Controller for low leakage, high speed and improved stability”Wireless Personal Communication, Springer, Septemeber 2016
  29. Rohit Lorenzo and Saurabh Chaudhury (2016),LCNT-An Approach to Minimize Leakage Power in CMOS Integrated Circuits”, Accepted in Microsystem Technologies,Springer, May 2016
  30. Robert Singh and Saurabh Chaudhury (2016). An Efficient Technique for Rice Grain Classification Using Back Propagation Neural Network and Wavelet Decomposition (Accepted) available online in IET Computer Vision, May 2016
  31. Rohit Lorenzo and Saurabh Chaudhury (2016). A novel Body Bias Conroller circuit for low leakage, reduced delay and improved stability. Journal of Circuit Systems and Computers,World Scientific Volume No.25, Issue No. 08..
  32. Rohit Lorenzo and Saurabh Chaudhury (2016). Review of Circuit level Leakage Minimization Techniques for VLSI Circuits and Systems. (Accepted) in IETE Technical Review (Taylor and Francis)
  33. Rohit Lorenzo and Saurabh Chaudhury (2016), “A NOVEL LOW LEAKAGE BODY BIASING TECHNIQUE FOR CMOS CIRCUITS”, Canadian Journal of Pure and Applied Sciences Vol. 10 , No. 1 , pp. 3827 – 3834 , February 2016
  34. Sanjeet Kumar Sinha, Saurabh Chaudhury (2015). Effect of Device Parameters on Carbon Nanotube Field Effect Transistor in Nanometer Regime, Journal of Nano Research,Vol. 36, p.64
  35. Rohit Lorenzo and Saurabh Chaudhury (2015). Body Biasing Scheme to Control Leakage, Speed and Stability in SRAM Cell Design. IJCA Proceedings on International Conference on Computing, Communication and Sensor Network CCSN 2014(1):11-15, June 2015.
  36. Sinha, Sanjeet Kumar, and Saurabh Chaudhury (2015). “Analysis of different parameters of channel material and temperature on threshold voltage of CNTFET.” Materials Science in Semiconductor Processing, Vol.31, pp. 431-438, Elsevier.
  37. S.K. Sinha, and S. Chaudhury (2014). Analytical approach to reduce leakage power in CNTFET over MOSFET device. Journal of Semiconductors, Vol.35, issue 11.
  38. S.K. Sinha, and S. Chaudhury (2014). Comparative Analysis of Leakage Power With 10 Nm Channel Length In MOSFET/CNTFET Devices. Journal of Electron Devices, Vol. 20, 2014, pp. 1718-1723.
  39. S.K. Sinha, and S. Chaudhury (2013). Impact of Oxide Thickness on Gate Capacitance-A Comprehensive Analysis on MOSFET, Nanowire FET and CNTFET Devices. IEEE Transaction on Nanotechnology. Vol. 12, Issue 6, pp958-964.
  40. S. Chaudhury, and A. K. Ray (2013). Histogram Equalization-A Simple but Efficient Technique for Image Enhancement. International Journal on Image, Graphics and Signal Processing. Vol. 5, Issue 10, MECS Press.
  41. S.K. Sinha, and S. Chaudhury (2013). Impact of Body Coefficient and Threshold Voltage on CNTFET with Varying Oxide Thickness. International Journal of Recent Development in Engineering and Technology (IJRDET). Vol. 1, Issue 1, pp 31-35.
  42. Sanjeet Kumar Sinha, Saurabh Chaudhury, “CNTFET based Logic Circuits: A Brief Review,” International Journal of Emerging Technology and Advance Engineering, Volume 2, Issue 4, pp-500-504, April 2012.
  43. Saurabh Chaudhury and Anirban Dutta, “Algorithmic Optimization of BDDs and Performance Evaluation for Multi-level Logic Circuits with Area and Power Trade-offs”, Circuits and Systems, Scientific Research Publication, Vol.2 No.3, 217-224, 2011.
  44. Saurabh Chaudhury, J. Srinivas Rao, Santanu Chattopadhyay, “State Assignment and Polarity Selection for Low Dynamic Power and Testable FSM Synthesis”, J. Low Power Electronics, ASP, Vol. No.3 Nov. 2009.
  45. Saurabh Chaudhury, Santanu Chattopadhyay, “Low Leakage FSM Synthesis with Area and Dynamic Power trade-offs”, Integration the VLSI Journal, Elsevier Volume 42 , Issue 3 pp376-384 June 2009.
  46. Saurabh Chaudhury, Santanu Chattopadhyay, “Fixed Polarity Reed-Muller Network Synthesis and its Application in AND-OR/XOR based circuit realization with Area-Power Trade-offs”, IETE Journal of Research Sept-Oct. 2008, Vol. 53.
  47. Saurabh Chaudhury, Santanu Chattopadhyay, “Output Phase Assignment for area and power minimization in PLAs”, J. Indian Inst. Sci. Jan-Feb 2006, 86, 33-43.

NATIONAL JOURNALS

INTERNATIONAL CONFERENCES

  1. Saurabh Chaudhury and Neerja Dharmale, “Pressure Induced Phase Transition study on brookite to rutile TiO2 Transformation”, 6th International conference on nanoscience and nanotechnology, 2021, SRMIST, Chennai, India, Feb. 01-03, 2021.
  2. Saurabh Chaudhury and Gaurahari Kaunr, “AUTOMATIC RECOGNITION OF INDIAN SIGN LANGUAGE USING IMAGE PROCESSING AND COMPUTER VISION” ICECET 2021, Cape Town, South Africa, 09-10 Dec. 2021
  3. Debashish Dash, Chandan K. Pandey, Saurabh Chaudhury, and S. K. Tripathy “ Structure and Electronic Properties of TiO2 Nanowires of Different Geometrical Shapes: An Ab-initio Study ,” 3rd IEEE International conference on Devices for Integrated Circuit (DevIC), 2019, Kolkata.
  4. Inamul Hussain, Chandan K. Pandey, and Saurabh Chaudhury, “Design and Analysis of Low Power Multiplier Circuit,” 3rd IEEE International conference on Devices for Integrated Circuit (DevIC), 2019, Kolkata.
  5. Avtar Singh, Chandan K. Pandey, Saurabh Chaudhury, and Chandan K Sarkar “Comparative Study of High K in Silicon Nano Tube FET for Switching Applications,” 3rd IEEE International conference on Devices for Integrated Circuit (DevIC), 2019, Kolkata.
  6. Chandan K. Pandey, Avtar Singh, and Saurabh Chaudhury, “Interfacial Charge Analysis of Dielectric Pocket SOI-TFET,” 3rd IEEE International conference on Devices for Integrated Circuit (DevIC), 2019, Kolkata.
  7. Chandan K. Pandey, and Saurabh Chaudhury, “A Novel Structure of Double-Gate Tunnel FET with Extended Back Gate for Improved Device Performances,” 2nd IEEE International conference on Innovations in Electronics, Signal processing and Communication (IESC), 2019, NIT Meghalaya.
  8. Chandan K. Pandey, Debashish Dash, and Saurabh Chaudhury, “Dielectric Engineered Tunnel FETs for Improved Device Performances,” 4th International conference on Nanotechnology-Applications, Advances and Innovations (NanoCon-2018), Oct. 25-26, BVDU, Pune.
  9. Chandan K. Pandey, and Saurabh Chaudhury, “Dual-Metal Graded-Channel Double-Gate Tunnel FETs for Reduction of Ambipolar Conduction,” 1st IEEE International conference on Electron Devices (EDKCON-2018), Nov. 24-25, Kolkata.
  10. D Debashish, C Saurabh, TS Kumar [2018]. A Density Functional Theory- Based Study of Electronic and Optical Properties of Anatase Titanium Dioxide, Int. Conference on Advances in Communication, Devices and networking, 2018
  11. Debashish Dash and Saurabh Chaudhury[2017], First Principle Investigation of Structural and Optical Properties of Cubic Titanium Dioxide, 2nd International conference on Condensed matter and Applied Physics, Dec. 2017, Bikaner, Rajasthan.
  12. Saurabh Chaudhury and Debashsish Dash, “A DFT based Strudy on Structural and Optical Properties of Pristine Pyrite Titanium Di-Oxide,” Int. Conference on Nanoscience and Nanotechnology (ICNSNT 2017), 14-15th Dec. 2017,Colombo
  13. Saurabh Chaudhury and Anindya Biswas,” Intelligent Traffic Control using Online Video Analysis,” Int. Conference on CCSN 2017, 30-31 Dec. 2017, Kolkata
  14. Rohit Lorenzo and Saurabh Chaudhury, “Low Leakage and Minimum Enery Consumption in CMOS logic Circuits”, IEEE Int. Conference EDCAV 2015, NIT Mehgalaya, Shillong, Jan.2015.
  15. Sanjeet Kumar Sinha and SaurabhChaudhury, “Advantage of CNTFET Characteristics Over MOSFET to Reduce Leakage Power”, 2nd IEEE International Conference on Devices, Circuits, and Systems (ICDCS 2014), Karunya University, Coimbatore, Tamilnadu, March6-8, 2014.
  16. Sanjeet Kumar Sinha, Preeti Singh and SaurabhChaudhury,” Effect of Temperature and Chiral Vector on Emerging CNTFET Device“, 8th IEEE International Conference on Computing for Sustainable Global Development (INDIACom 2014) March 5-7, 2014, BhartiVidyapeeth, New Delhi.
  17. RohitLorenzo and SaurabhChaudhury , “A Novel PMOS Data Retention Leakage Power Reduction Design” International Conference on Communication Systems and Network Technologies (CSNT-2014), April 7-9, 2014 NITTTR Bhopal.
  18. RohitLorenzo and SaurabhChaudhury , “Analysis of leakage feedback techniques” Proceedings of IEEE International conference on Electronics communication and Instrumentation 2014 16-17 January 2014 organized by Heritage Institute of Technology ,Kolkata (WB).
  19. Sanjeet Kumar Sinha and SaurabhChaudhury,”Application ofGraphene as CNT in CNTFET Devices”, 10th National Conference on Solid State Ionics (NCSSI-10), IIT Kharagpur, W.B, India, December 22-24, 2013.
  20. Sanjeet Kumar Sinha and SaurabhChaudhury, “Impact of Temperature Variation on CNTFET Device Characteristics”, IEEE International Conference on Control, Automation, Robotics & Embedded Systems (CARE-2013), IIIT-DM Jabalpur, M. P, India, December 16-18, 2013, pp. 1-5.
  21. Sanjeet Kumar Sinha, Kanhaiya Kumar and SaurabhChaudhury,” CNTFET: The Emerging Post- CMOS Device”, IEEE International Conference on Signal Processing and Communication (ICSC 2013), JIIT Noida, U.P, December12-14, 2013, pp. 372-374.
  22. Sanjeet Kumar Sinha and SaurabhChaudhury, “CNTFET: The Emerging device in nanometer Regime”, International Conference on Advanced nanomaterials and nanotechnology (ICANN-2013), IIT Guwahati, India, December1-3,2013.
  23. Sanjeet Kumar Sinha and SaurabhChaudhury, “A Comparative Analysis of FETToy Simulation of CNTFET Characteristics”, IEEE International Conference on Emerging Trends and Applications in Computer Science (ICETACS – 2013), Shillong, Meghalaya, India, September 13-14, 2013, pp62-64.
  24. Rohit Lorenzo and SaurabhChaudhury , “A Novel all NMOS leakage feedback with data retention technique” Proceedings of IEEE sponsored International conference on Control, Automation,Robotics and Embedded system December 16-18,2013 organized by PDPM IIITDM Jabalpur (MP).
  25. Sanjeet Kumar Sinha and S. Chaudhury,” Simulation and Analysis of Quantum Capacitance in Single-Gate MOSFET, Double-Gate MOSFET and CNTFET devices for Nanometre Regime” IEEE International Conference on Communication, Devices and Intelligent Systems : (CODIS 2012), Jadavpur University (JU) , Kolkata, India, 28-29 December, 2012, pp. 157-160.
  26. Sanjeet Kumar Sinha and S. Chaudhury,” Oxide thickness effect on Quantum Capacitance in single gate MOSFET and CNTFET devices,” 2012 Annual IEEE India Conference (INDICON-2012), Ernakulam, Kerala, India, 7-9 Dec. 2012, pp. 042-046.
  27. Sanjeet Kumar Sinha and S. Chaudhury,” Advantage of Carbon Nannotube Field Effect Transistor (CNTFET) over Double-Gate MOSFET in Nanometre Regime,” IEEE National Conference on Computing and Communication Ststems (NCCCS-2012), Durgapur, India, 21-22 Nov. 2012, pp.1-5.
  28. Sanjeet Kumar Sinha and S. Chaudhury,” Analysis of Quantum Capacitance for single gate MOSFET, Double gate MOSFET, Silicon nanowire MOSFET and CNTFET Devices in nanometer regime with varied Oxide Thickness,” II International Conference nanotechnology- Innovative materials, Processes, Products and Applications (NANOCON 012), Pune , Maharastra, India, 18-19 Oct. 2012, pp. 1133-1143.
  29. Sanjeet Kumar Sinha and S. Chaudhury, ”Quantum Capacitance: The deciding factor in nanometer regime for CNTFET,” 2012 IEEE International Conference on Advanced Communication, Control & Computing Technologies (ICACCCT-2012), Ramanathapuram, Tamilnadu, India, 23-25 August 2012, pp. 243-247.
  30. Saurabh Chaudhury and Anirban Sengupta, “Designing a Digital Filter Bank and an Adaptive Filtering Technique to Eliminating Noises in power Line Communication”, In the Proc. of IEEE PEAM 2012, 14-16 Sept. 2012, Wuhan, China.
  31. Suman Deb and Saurabh Chaudhury, “High Speed Comparator Architectures for Fast Binary Comparison,” Int. Conf. CSI-EAIT, Dec. 2012, Kolkata.
  32. Saurabh Chaudhury, Anirban Dutta, “Genetic Algorithm based variable ordering of BDDs for multi-level logic synthesis with area and power trade-offs”, in IEEE ICECS 12-15 Dec. 2010, Athens, Greece.
  33. Saurabh Chaudhury, Indrani Pal, “A New Approach to Image Segmentation with MATLAB”, in ICCCT 2010, Allahabad, India.
  34. Saurabh Chaudhury, Santanu Chattopadhyay, “Output Phase Assignment for Area and Power Optimization in Multi-level Multi-output Combinational Logic Circuits”, IEEE INDICON 2006, New Delhi.
  35. Saurabh Chaudhury, J. Srinivas Rao, Santanu Chattopadhyay, “Synthesis of Finite State Machines for Low Power and Testability”, IEEE APCCAS 2006, Dec.4-7 Singapore.
  36. Saurabh Chaudhury, Krishna Teja S., Santanu Chattopadhyay, “Synthesis of Finite State Machines for Low Static and Dynamic Power”, ISIC 2007, Sept.26-28, Singapore.
  37. Saurabh Chaudhury, Krishna Teja S., Santanu Chattopadhyay, “State Encoding Targeting Low Area and Low Power FSM Synthesis”, IEEE VLSI Design and Test Symposium, VDAT 2007, August 8-11 , Kolkata.
  38. Saurabh Chaudhury, Ansuman Prusty, Santanu Chattopadhyay, “A Genetic Algorithm based Input State Assignment Technique for Leakage Power Minimization in Combinational Logic Circuits,” ADCOM 2007, Dec.17-20, IIT Guwahati.
  39. Saurabh Chaudhury and Santanu Chattopadhyay, “Leakage-aware Synthesis of Multi-level logic Circuits based on BDD Manipulation and Output Phase Assignment”, VDAT 2008 Bangalore.

BOOK CHAPTER

  • “Genetic Algorithms for Low Power Logic Optimization and Synthesis, by Saurabh Chaudhury, Publisher-Scholar’s Press, Germany, 2013.
  • Saurabh Chaudhury and Rohit Lorenzo (2016),”Leakage Minimization in CMOS VLSI Circuits-A Brief Review”, IGI Global Publications, June 2016, DOI: 10.4018/978-1-5225-0190-9.ch004.
  • Saurabh Chaudhury and Sanjeet K Sinha, ” Carbon Nanotube Field-Effect Transistor: The Application of Carbon Nanotube ” CRC Press 2015, Print ISBN: 978-1-4822-5394-8, eBook ISBN: 978-1-4822-5396-2.
  • Jayesh Ruikar, Saurabh Chaudhury, A.K Sinha, Image Quality Assessment with Structural Similarity Using Wavelet Families at Various Decompositions, Springer india 2016
  • Effect of Ground Plane and Strained Silicon on Nanoscale FET Devices, Avtar Singh and Saurabh Chaudhury, in the book Nano-Scale Device Physics (CRC Press) 2018.
  • Carbon Nanotube and Nanowires for Future Semiconductor Devices Applications, Saurabh Chaudhury and Sanjeet k. Sinha, in the book Nanoelectronics: Devices, Circuits and systems, 2018, DOI: 10.1016/B978-0-12-813353-8.00014-2.
  • Ksh. Robert Singh & Saurabh Chaudhury, “Texture analysis for rice grain classification using wavelet decomposition and back propagation neural network”. Learning and Analytics in Intelligent Systems, 2020, Springer (book chapter) , ISBN: 978-3-030-42362-9, vol-12, pp. 55-65.

PROJECTS

WORKSHOPS ORGANIZED

CONFERENCE ORGANIZED

PHD SCHOLARS

Sl. No. Name of the Scholar Status Research Area Supervision
1 Ongoing Sole Supervisor
2 Ongoing Sole Supervisor
3 Ongoing Sole Supervisor
4 Ongoing Sole Supervisor
5 Ongoing Sole Supervisor

M.TECH. SCHOLARS

Sl. No. Name of Scholar Status Thesis Title Supervision